direct rambus? clock generator (lite) cy2212 cypress semiconductor corporation 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07466 rev. ** revised december 9, 2002 features benefits ? direct rambus? clock support one pair of differential output drivers high-speed clock support 400-mhz maximum, 300-mhz minimum output frequency input select option pll multiplier select crystal oscillator divider output lclk = xtal/2, not driven by phase-locked loop (pll) output edge-rate control minimize emi 16-pin tssop space-saving, low-cost package logic block diagram 16-pin tssop 1 2 3 4 5 6 7 8 9 12 11 10 13 16 15 14 cy2212 clkb clk s xin xout pll xtal oscillator lclk xm /2 top view clk vdd s nc vss clkb vss vdd xin vssl vddp nc lclk vddl xout vssp xtal value = 18.75 mhz pin configuration frequency select table s m (pll multiplier) clk,clkb lclk 0 16 300 mhz 9.375 mhz 1 64/3 400 mhz 9.375 mhz
cy2212 document #: 38-07466 rev. ** page 2 of 10 absolute maximum conditions crystal requirements these are the requirements for the recommended crystal to be used with the cy2212 drcg lite clock source. the crystal type is parallel resonant. the mode is fundamental. internal capacitors will not be implemented in the crystal oscillator circuit. external capacitors will be needed. notes: 1. at 25 c 3 c. 2. cl = 10 pf. 3. ? 10 c to 75 c. 4. at x f 500 khz. pin description name pin description vddp 1 3.3v power supply for pll vssp 2 ground for pll xout 3 reference crystal feedback xin 4 reference crystal input vddl 5 1.8v power supply for lclk lclk 6 lvcmos output, x1/2 crystal frequency vssl 7 ground for lclk nc 8 no connect (reserved for test mode) nc 9 no connect (reserved for test mode) vdd 10 3.3v power supply vss 11 ground clkb 12 output clock (complement), connect to rambus channel clk 13 output clock, connect to rambus channel vss 14 ground vdd 15 3.3v power supply s 16 pll multiplier select input, pull-up resistor internal parameter description min. max. unit v dd,abs max. voltage on v dd , v ddp , or v ddl with respect to ground ? 0.5 4.0 v v i, abs max. voltage on any pin with respect to ground ? 0.5 v dd + 0.5 v v il, abs max. voltage on lclk with respect to ground ? 0.5 v ddl + 0.5 v parameter description min. max. unit x f frequency 14.0625 18.75 mhz x ftol frequency tolerance [1] ? 15 15 ppm x eqres equivalent resistance [2] 100 ? x temp temperature drift [3] 10 ppm x drive drive level 0.01 1500 w x mi motional inductance 20.7 25.3 mh x ir insulation resistance 500 m ? x sar spurious attenuation ratio [4] 3db x os overtone spurious 8 db
cy2212 document #: 38-07466 rev. ** page 3 of 10 state transition characteristics specifies the maximum settling time of the clk, clkb, and lclk outputs from device power-up. for v dd , v ddp , and v ddl any sequences are allowed to power-up and power-down the cy2212 drcg-lite. dc electrical specifications parameter description min. max. unit v dd supply voltage 3.04 3.56 v v ddl lclk supply voltage 1.7 2.1 v t a ambient operating temperature 0 70 c v il input signal low voltage at pin s 0.35 v dd v ih input signal high voltage at pin s 0.65 v dd r pup internal pull-up resistance 10 100 k ? ac electrical specifications parameter description min. max. unit f xtal,in input frequency at crystal input [5] 14.0625 18.75 mhz c in,cmos input capacitance at s pin [6] 10 pf dc device specifications parameter description min. max. unit v cm differential output common-mode voltage 1.35 1.75 v v x differential output crossing-point voltage 1.25 1.85 v v cos output voltage swing (p-p single-ended) [7] 0.4 0.7 v v coh output high voltage 2.1 v v col output low voltage 1.0 v r out output dynamic resistance (at pins) [8] 12 50 ? v loh lclk output high voltage at i oh = ? 10 ma v ddl ? 0.45v v ddl v v lol lclk output low voltage at i ol = 10 ma 0 0.45 v from to transition latency description v dd /v ddl /v ddp on clk/clkb/lclk normal 3 ms time from v dd /v ddl /v ddp is applied and settled to clk/clkb/lclk outputs settled ac device specifications parameter description min. max. unit t cycle clock cycle time 2.5 3.33 ns t j jitter over 1 ? 6 clock cycles at 400 mhz [9] 100 ps jitter over 1 ? 6 clock cycles at 300 mhz [9] 140 ps t jl long-term jitter at 400 mhz 300 ps long-term jitter at 300 mhz 400 ps dc long-term average output duty cycle 45% 55% t cycle t dc,err cycle-cycle duty cycle error at 400 mhz 50 ps cycle-cycle duty cycle error at 300 mhz 70 ps notes: 5. nominal condition with 18.75-mhz crystal. 6. capacitance measured at freq = 1 mhz, dc bias = 0.9 v, and vac < 100 mv. 7. v cos = v oh ? v ol . 8. r out = ? v o / ? i o . this is defined at the output pins, not at the measurement point of figure 3 . 9. output short-term jitter specification is peak-peak and defined in figure 10 .
cy2212 document #: 38-07466 rev. ** page 4 of 10 functional specifications this section gives the detailed functional specifications of the device physical layer. these specifications refer to the logical and physical interfaces. crystal input the cy2212 receives its reference from an external crystal. pin xin is the reference crystal input, and pin xout is the reference crystal feedback. the parameters for the crystal are given on page 3 of this data sheet. select input there is only one select input, pin s. this pin selects the frequency multiplier in the pll, and is a standard lvcmos input. the s pin has an internal pull-up resistor. the multiplier selection is given on page 1 of this data sheet. lclk output driver in addition to the rambus clock driver outputs, there is another clock output driver. the lclk driver is a standard lvcmos output driver. figure 1 below shows the lclk output driver load circuit. rsl clock output driver figure 2 shows the clock driver equivalent circuit. the differential driver has a low output impedance in the range of about 20 ohms. the driver also produces a specified voltage swing on the channel. the nominal value of the channel impedance, z ch , is 28 ohms. series resistor rs and parallel resistor rp are used to set the voltage swing on the channel. the driver output characteristics are defined together with the external components, and the output clock is specified at the measurement point indicated in figure 2 . the complete set of external components for the output driver, including edge-rate filter capacitors required for system operation, are shown in figure 3 . the values for the external components are given in table 1 . the output clocks drive transmission lines, potentially long lines. since circuit board traces will act as lossy, imperfectly terminated transmission lines with some discontinuities, there will be reflections generated which will travel back to the drcg-lite output driver. if the output impedance does not match zch, secondary reflections will be generated that will add to position-dependent timing uncertainty. therefore, the cy2212 not only provides proper output voltage swings, but also provides a well-matched output impedance. the driver impedance, r out , is in series with r s , and the combination is in parallel with r p . notes: 10. lclk cycle jitter and 10-cycle jitter are defined as the difference between the measured period and the nominal period as de fined on page 8. 11. lclk 10-cycle jitter specification is based on the measured value of lclk cycle jitter as defined on page 8. t cr , t cf output rise and fall times (measured at 20% ? 80% of output voltage) 250 500 ps t cr, cf difference between output rise and fall times on the same pin of a single device (20% ? 80%) 100 ps bw loop pll loop bandwidth 50 khz ( ? 3 db) 8 mhz ( ? 20 db) t cycle,l lclk clock cycle time 106.6 142.2 ns t lr , t lf lclk output rise and fall time 1 ns t jc,l lclk cycle jitter [10] ? 0.8 0.8 ns t j10,l lclk 10-cycle jitter [10,11] ? 1.1 * t jc,l 1.1 * t jc,l ns dc l lclk output duty cycle 40% 60% t cycle,l ac device specifications (continued) parameter description min. max. unit 120 ? 120 ? 10 pf lclk figure 1. lclk test load circuit r s r s r p r p z ch z ch r t = z ch r t = z ch measurement point measurement point differential driver figure 2. equivalent circuit
cy2212 document #: 38-07466 rev. ** page 5 of 10 the clock driver is specified as a black-box at the packaged pins. the output characteristics are measured after the series resistance, r s . the outputs are terminated differentially, with no applied termination voltage. figure 3 below shows the clock driver implemented as a push- pull driver. when stimulating the output driver, the trans- mission lines shown in figure 3 can be replaced by a direct connection to the termination resistors, r t . the values for the external components are given in table 1 . as mentioned previously, the clock driver ? s output impedance matches the channel impedance. to accomplish this, each of the output driver devices are sized to have an r out of about 20 ohms when fully turned on. r out is the dynamic output resistance, and is defined in the dc device characteristics table on page 3 of this data sheet. since r out is in series with r s , and that combination is in parallel with r p , the effective output impedance is given by: r p (r s + r out )/(r p + r s + r out ). this calculation results in a effective output impedance of about 27 ohms for the values listed in table 1 . since the total impedance is dominated by the external resistors, a large possible range of r out is allowed. when the output is transi- tioning, the impedance of the cmos devices increases dramatically. the purpose of r p is to limit the maximum output impedance during output transitions. in order to control signal attenuation and emi, clock signal rise/fall times must be tightly controlled. therefore, external filter capacitors c f are used to control the output slew rate. in addition, the capacitor c mid is used to provide ac ground at the mid-point of the r p resistors. table 1 gives the nominal values of the external components and their maximum acceptable tolerance, assuming zch = 28 ohms. table 1. output external component values parameter description value tolerance unit r s series resistor 68 5% ohm r p parallel resistor 39 5% ohm c f edge-rate filter capacitor 15 10% pf c mid ac ground capacitor 0.01 20% f r s r s r p r p z ch z ch r t =z ch r t =z ch measurement point measurement point drcg lite c f c f c mid c mid figure 3. output driver r s r s r p r p z ch z ch r t = z ch r t = z ch measurement point drcg lite c f c f c mid c mid z ch z ch r t = z ch r t = z ch measurement point c mid r x r x r x r x figure 4. output driving two channels
cy2212 document #: 38-07466 rev. ** page 6 of 10 dual-channel output driver figure 4 shows the clock driver driving two high-impedance channels. the purpose of the series resistors r x is to de- couple the two-channels, and prevent noise from one channel from coupling onto the second channel. with z ch = 40 ohms and the series resistor set to r x = 16 ohms, the channel becomes an effective 56-ohm channel. the two channels in parallel can be treated as a single 28-ohm channel, and all of the external component values listed in table 1 can be used. signal waveforms a physical signal which appears at the pins of the device is deemed valid or invalid depending on its voltage and timing relations with other signals. this section defines the voltage and timing waveforms for the input and output pins of the cy2212. the device characteristics tables list the specifica- tions for the device parameters that are defined here. input and output voltage waveforms are defined as shown in figure 5 . both rise and fall times are defined between the 20% and 80% points of the voltage swing, with the swing defined as v h ? v l . for example, the output voltage swing v cos =v oh ? v ol . the device parameters defined according to figure 5 are as follows. figure 6 shows the definition of output crossing point. the nominal crossing point between the complementary outputs is defined to be at the 50% point of the dc voltage levels. there are two crossing points defined, vx+ at the rising edge of clk and vx ? at the falling edge of clk. for some clock waveforms, both vx+ and vx ? might be below vx, nom (for example, if t cr is larger than t cf ). vx is defined as the differential output crossing point voltage. figure 7 shows the definition of long-term duty cycle, which is simply the waveform high-time divided by the cycle time (defined at the crossing point). long-term duty cycle is the average over many (>10,000) cycles. short-term duty cycle is defined in the next section. dc is defined as the output clock long-term duty cycle. jitter this section defines the specifications that relate to timing uncertainty (or jitter) of the input and output waveforms. figure 8 shows the definition of long-term jitter with respect to the falling edge of the clk signal. long-term jitter is the difference between the minimum and maximum cycle times. equal requirements apply for rising edges of the clk signal. t jl is defined as the output long-term jitter. table 2. definition of device parameters parameter definition v oh , v ol clock output high and low voltages v cos clock output swing v cos = v oh ? v ol v cm common-mode voltage v cm = (v oh ? v ol )/2 v ih , v il vdd lvcmos input high and low voltages t cr , t cf clock output rise and fall times t cr , c f clock output rise/fall time delta t cr,cf = t cr ? t cf t cr t cf v(t) v oh 80% 20% v ol figure 5. voltage waveforms clk clkb vx+ vx ? vx,nom figure 6. crossing-point voltage
cy2212 document #: 38-07466 rev. ** page 7 of 10 figure 9 shows the definition of cycle-to-cycle jitter with respect to the falling edge of the clk signal. cycle-to-cycle jitter is the difference between cycle times of adjacent cycles. equal requirements apply for rising edges of the clk signal. t j is defined as the clock output cycle-to-cycle jitter. figure 10 shows the definition of four-cycle short-term jitter. short-term jitter is defined with respect to the falling edge of the clk. four-cycle short-term jitter is the difference between the cumulative cycle times of adjacent four cycles. equal requirements apply for rising edges of the clk signal. equal requirements also apply for two-cycle short-term jitter and three-cycle short-term jitter, and for five-cycle short-term jitter and six-cycle short-term jitter. t j is defined as the clock output short-term jitter over 2, 3, 4, 5, or 6 cycles. the purpose of this definition of short-term jitter is to define errors in the measured time (for example, t 4cycle,i ) vs. the expected time. the purpose for measuring the adjacent time t 4cycle, i+1 is only to help determine the expected time for t 4cycle, i . alternate methods of determining t j are possible, including comparing the measured time to an expected time based on a local cycle time, t cycle,local . this local cycle time could be determined by taking the rolling average of a group of cycles (5 ? 10 cycles) proceeding the measured cycles. however, it is important to differentiate this rolling average from the average cycle time, t cycle,avg , which is the average cycle time over the 10,000 cycles. using a long-term average instead of a rolling average would define t j as a long-term jitter instead of a short-term jitter, and would normally giver overly pessimistic results. figure 11 shows the definition of cycle-to-cycle duty cycle error. cycle-to-cycle duty cycle error is defined as the difference between high-times of adjacent cycles. equal requirements apply to the low-times. t dc , err is defined as the clock output cycle-to-cycle duty cycle error. t pw+ t cycle clk clkb dc = t pw + /t cycle figure 7. duty cycle t cycle t jl = t cycle,max ? t cycle,min over 10000 cycles clk clkb figure 8. long-term jitter t cycle,i t j = t cylce,i ? t cycle,i + 1 over 10000 consecutive cycles clk clkb t cycle,i+1 figure 9. cycle-to-cycle jitter
cy2212 document #: 38-07466 rev. ** page 8 of 10 figure 12 shows the definition of lclk cycle jitter and lclk 10-cycle jitter. these parameters apply to the lclk output, and not to the rambus channel clock outputs. lclk cycle jitter is the variation in the clock period, t, over a continuous set of clock cycles. the difference between the maximum period and the nominal period in the set of clock cycles measured would be compared to the max spec listed in the ac device characteristics table on page 3. lclk cycle jitter is measured between rising edges at 50% of the output voltage, and is measured continuously over 30,000 cycles. lclk 10-cycle jitter is the variation in the time of 10 clock cycles, 10*t, where t is the clock period. the difference between the maximum 10-cycle period and the nominal 10- cycle period in the set of clock cycles measured would be compared to the max spec listed in the ac device character- istics table on page 5. note that the specification for lclk 10- cycle jitter is defined based on the measured value of lclk cycle jitter. lclk 10-cycle jitter is measured between the first rising edge and the tenth rising edge at 50% of the output voltage, and is measured over 30,000 continuous cycles. t jc,l is defined as the lclk output cycle jitter, and t j10,l is defined as the lclk output jitter over 10 cycles. measurement the short-term jitter specification (over one to six cycles) for the clock source is given as t j , as previously shown. jitter should be measured using a jitter measurement system that has the flexibility of measuring cycle-to-cycle jitter as a function of cycle count. it is important that the short-term jitter be measured over consecutive cycles in order to prevent long- term drift from causing overly-pessimistic results. when measured over 10,000 consecutive cycles, the short-term jitter measurements generate large amounts of data which can be viewed in a histogram. figure 13 shows an example histogram of data from a 4-cycle short-term jitter measurement, with results that are within spec lines for t j . note that the jitter is specified as peak-to-peak, so the center of the histogram need not be exactly zero. further details of jitter measurement methodologies are given in the rambus drcg-lite specification appendix a published by rambus, inc. t 4cycle,i t 4cycle,i+1 t j = t 4cycle,i ? t 4cycle,i+1 over 10000 consecutive cycles clk clkb figure 10. short-term jitter t pw+,i t dc,err = t pw+,i ? t pw+,i+1 clk clkb t pw+,i+1 t cycle,i+1 t cycle,i+1 cycle i cycle i+1 figure 11. cycle-to-cycle duty cycle error lclk t 10*t figure 12. lclk jitter
cy2212 document #: 38-07466 rev. ** page 9 of 10 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. ordering information rambus, rdram, and the rambus logo are registered trademarks of rambus inc. direct rambus, rimm, sorimm, and direct rdram are trademarks of rambus, inc. 4 cycle jitter jitter spec figure 13. example jitter measurement histogram ordering code package name package type operating range cy2212zc-1 z16 16-lead tssop commercial CY2212ZC-1T z16 16-lead tssop ? tape and reel commercial package drawing and dimensions 16-lead thin shrunk small outline package (4.40-mm body) z16 51-85091-**
cy2212 document #: 38-07466 rev. ** page 10 of 10 document history page document title: cy2212 direct rambus tm clock generator (lite) document number: 38-07466 rev. ecn no. issue date orig. of change description of change ** 117801 12/10/02 ckn new data sheet
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